The Computerbury Tales

General Prologue

When the Vaxen with their markets pooped,
The swarms of RISC hath made their beauty moot,
And bathed every system in such high power,
Which engendered the Architect's ardor;

When journals with their reviewers' teeth,
Inspired fear in DEC's elite,
The young Radicals, and there are some,
Hath RISC in hand, and had some fun.

But the Managers made as if to flee,
Forsaking the new technology,
As if the Vaxen were entrenched,
So no such clever chip,
Could save the company.

It happened, an assignment on a day,
In Usenet, at comp.arch as I lay,
Ready to begin another flame,
On architecture, my knowledge lame,
An email happened to arrive; Creativity, it was said,
Does not substitute for the thread
Of clarity and knowledge.

"But amuse me if you must",
The Professor said; I trust,
This tale is appropriate and informed,
So as to raise the level of the norm,
And educate, if not to please.

I think it of good reason,
To tell you of the condition
Of architecture, in nineteen-ninety-three,
How RISC cheered, "I've won, I've won!"
As CISC goes to the garbage bin,
So it is with Alpha I begin.

The Alpha's Tale

All round the Alpha gathered we,
No tale of woe or misery
Would taint this young'ns tale,
Not one year old, he hails
from DEC, yet can outrun
Every other solution,
And so begins his story.

"The Architects, of my homeland DEC,
Were mired, entrapped in dreck,
Of VAX compatibility.
They assumed the liability
Of a new chip, a bold approach,
But to be beyond reproach,
They needed to port old VMS,
(an OS in extreme duress)
Cleanly and with no compromise.

A binary translator, they soon found,
Was technologically sound,
Since microcode was no longer nice,
They took the industry's good advice,
and looked ahead to see what they would need.

'Two hundred MHz', they did accede,
'And three orders of magnitude
Improvement in its fortitude
Over a quarter century
Would be more than plenty
To ensure a market lead.'

Spartan was my birth indeed,
No lot of warts and stuff,
Only what was just enough
For scalability and speed.
No arithmetic traps in hardware, please,
Software does it just as well,
And does not cause the alarum bell
To ring, unless you so assign.

Like the other RISC designs,
Operations are quite short and small,
Load/Store, Branch and ALU, that's all,
But for the clever PAL,
With primitives, they do tell,
Not quite like microcode, they are routines
Privileged for that software queen,
The operating system. Changed they can be,
To benefit systems not yet conceived,
Or languages that will leave you peeved,
Without bias; all are welcome here.

Sixty four bits allays the fear,
Of addresses which exhaust the clout
Of processors, at about
Six tenths of a bit a year; this chip,
Would never cast a doubt, a blip
Of falling to the evil ways
Of segmentation, or other forays
Into doom, like Precision Architecture did.

Multiple instruction launch, a bid
For tenfold bettering, in time,
Of execution of a program, mine
To have with better compilers,
And a scaled up design. Aside from that,
A faster clock would give another
Improvement in speed, but another
Factor of ten would be desired.

Parallel machines are all the rage, but mired,
In difficult synchronization grief,
Yet that extra speed, it is their belief,
Comes from more of us, it seems,
So the Architects, inspired by some dream,
Gave me a unique interlocking scheme,
That works with the fastest caches,
(Though this subject is one which clashes
With the well-being of my poor brain.)